`timescale 1ns/1ps

`ifndef __ISE__
`include "code\source\P3\nco_naive.v"
`endif 

module test_nco_naive;

`ifndef __ISE__
initial begin    
    $dumpfile("./release/test_nco_naive.vcd");
    $dumpvars(0, test_nco_naive);
end
`endif

// Generate clock
reg clk;
initial clk = 0;
always #1 clk = ~clk;

// Input registers
reg reset, load;
reg [31:0] fcw;
// Output wires
wire out_valid;
wire [11:0] out;
// TB Variable

wire [14:0] lut_addr;
wire [11:0] lut_data;
reg [11:0] lut_mem [0:32768];

initial begin
    $readmemb("D:/programming/verilog/Digital_Communication_SelfTest/code/test/P3/code_lut.txt", lut_mem);
end

assign lut_data = lut_mem[lut_addr];

task set_fcw(input [31:0] _fcw);
    begin
        $display("set_fcw: %d", _fcw);
        @(negedge clk);
        fcw = _fcw;
        load = 1;
        @(negedge clk);
        load = 0;
    end
endtask

initial begin
    reset = 1;
    load = 0;
    fcw = 0;
    @(negedge clk);
    reset = 0;
    repeat(2) @(posedge  clk);

    set_fcw(10000000);
    repeat(2000) @(posedge  clk);

    set_fcw(20000000);
    repeat(2000) @(posedge  clk);

    set_fcw(0);
    repeat(100) @(posedge  clk);
    // Exit the simulation
    $finish;
end

always@(negedge clk) begin
    if (out_valid) begin
        $display("%d", out);
    end
end

// Device under test (our adder)
nco_naive dut (.rst_n(~reset), .clk(clk), .fcw(fcw), .load(load), .out(out), .out_valid(out_valid), .lut_data(lut_data), .lut_addr(lut_addr));

endmodule
